This invention relates to latch circuits in semiconductor integrated circuit devices, and more particularly to a latch circuit for use with a single-wire clock.
In semiconductor integrated circuit devices, such as microprocessors or memory circuits, various clocks must be made available at many points on the chip. Delays and intercoupling cause the clocks to become skewed, especially when multiple-phase clocks are employed.
It has previously been the practice in CMOS latches to use true and complement clocks to clock the PMOS and NMOS devices in each latch. The function of complementing (inverting) the clock voltage causes an inherent skew, and so the conventional CMOS latches are prone to the "race-through" problem.
A method of alleviating the race-through problem is to feed the single-wire clock to one type of device only, in each latch-the clock going to N-channel transistors in the master latch and P-channel transistors in the slave latch. Generally, it is preferable to have the clock and data inputs feeding the gates of MOS transistors, thus providing an high impedance input. Also, it is preferable to have the outputs of the latches to be non-dynamic nodes.
Another drawback to prior implementations of CMOS latches is that NMOS devices alone do not pass good "1" levels, and PMOS devices alone do not pass good zero levels. To help restore the level to a full rail, feedback can be employed, but this will in general lead to DC rationing between the clocked device and the feedback device. Alternatively, multistage latches can be employed which do not have DC ratioing; however, such latches normally incur an undue number of gate delays from input to output, and are complex, requiring a large number of transistor devices to accomplish the function.